A process (so-called damascene process), which involves filling a metal (interconnect material) into interconnect trenches and via holes, is currently being used as a process for the formation of interconnects of a semiconductor device. The process technology involves filling a metal such as aluminum, or more recently copper or silver, into interconnect trenches and via holes previously formed in an interlayer dielectric, and then removing an extra metal by chemical mechanical polishing (CMP) into a flat surface.
FIGS. 1A through 1D illustrate, in a sequence of process steps, an exemplary process for forming copper interconnects in a semiconductor device. First, as shown in FIG. 1A, an insulating film (interlayer dielectric) 2, e.g., an SiO2 oxide film or a film of low-k material, is deposited on a conductive layer 1a, in which semiconductor elements have been formed, on a semiconductor base 1; via holes 3 and interconnect trenches 4 as interconnect recesses are formed in the insulating film 2, e.g., by the lithography/etching technique; and, e.g., by sputtering, a barrier layer 5 of TaN or the like is formed on an entire surface and a seed layer 6, which serves as a feeding layer during electroplating, is formed on the barrier layer 5.
Subsequently, as shown in FIG. 1B, copper plating is carried out on a surface of a wafer (polishing object) W to deposit a copper film 7 on the insulating film 2 while filling copper into the via holes 3 and the interconnect trenches 4 of the wafer W. Thereafter, as shown in FIG. 1C, the seed layer 6 and the copper film 7 on the barrier layer 5 are removed, e.g., by chemical mechanical polishing (CMP) until the surface of the barrier layer 5 becomes exposed and, as shown in FIG. 1D, the barrier layer 5 on the insulating film 2 and, if necessary, a surface portion of the insulating film 2 are removed, thereby forming interconnects (copper interconnects) 8 composed of the seed layer 6 and the copper film 7 in the insulating film 2.
A polishing apparatus which, in order to increase the throughput, is provided with two polishing lines and one cleaning line has been developed. In such a polishing apparatus, wafers (polishing objects) after polishing are sequentially supplied from two polishing lines to one cleaning line. In this case, when a wafer has entered into a cleaning process, another wafer cannot enter into a cleaning process until the termination of the preceding cleaning process. Thus, a situation occurs in which cleaning of a wafer after polishing cannot be started immediately after the polishing, and the wafer must stand-by until a cleaning machine becomes available.
In a metal film polishing process, for example, a copper film polishing process in the above-described process for the formation of copper interconnects, if a wafer after polishing is left as it is in a wet state, corrosion of copper, constituting copper interconnects of a semiconductor circuit in the surface of the wafer, will progress. The corrosion of the copper interconnects leads to an increase in the resistance, and therefore must be avoided as much as possible.
In order to retard progress of corrosion of copper, constituting copper interconnects of a wafer, during the period after the termination of polishing until the start of cleaning, it is a common practice to supply pure water to a surface of the wafer so that the wafer surface after polishing may not be directly exposed to the air. This method, however, cannot fully prevent corrosion of copper. In order to fully prevent corrosion of copper, it is required to minimize the time period from the termination of polishing to the start of cleaning.
Schedulers for controlling the process of transport, processing and cleaning of a wafer in, e.g., a wafer processing apparatus have been proposed (see Published Japanese Translation of International Patent Publication Nos. 2004-526263 and 2002-511193, and International Patent Publication No. 01/054187 Pamphlet).